1. Technical Field
The present invention generally relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and an operating method thereof.
2. Related Art
In general, a semiconductor memory device is classified into a volatile memory device and a nonvolatile memory device. The volatile memory device loses data stored therein when power supply is cut off, but the nonvolatile memory device maintains data stored therein even though power supply is cut off. The nonvolatile memory device may include various types of memory cells.
The nonvolatile memory device may be divided into a flash memory device, a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase change memory device using chalcogenide alloys, a resistive RAM (ReRAM) using transition metal oxide and the like, depending on the structure of memory cells.
Among the nonvolatile memory devices, the flash memory device is roughly divided into a NOR flash memory device and a NAND flash memory device, depending on the connection state between memory cells and a bit line. The NOR flash memory device has a structure in which two or more memory cell transistors are connected in parallel to one bit line. Therefore, the NOR flash memory device has an excellent random access time characteristic. On the other hand, the NAND flash memory device has a structure in which two or more memory cell transistors are connected in series to one bit line. Such a structure is referred to as a cell string, and one bit line contact is required per one cell string. Therefore, the NAND flash memory device has an excellent characteristic in terms of integration degree.
Among the nonvolatile memory devices, a flash memory device uses an input/output (I/O) multiplexing method. That is, commands and addresses as well as data are provided to the flash memory device through data I/O pins (or pads). In order to use the v multiplexing method, the flash memory device may determine which signal is applied through the data I/O pins (or pads) through a combination of input control signals.